High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Implementation of AES-GCM encryption algorithm for high performance and low power architecture Using FPGA

Evaluation of the Advanced Encryption Standard (AES) algorithm in FPGA is proposed here. This Evaluation is compared with other works to show the efficiency. Here we are concerned about two major purposes. The first is to define some of the terms and concepts behind basic cryptographic methods, and to offer a way to compare the myriad cryptographic schemes in use today. The second is to provide...

متن کامل

RFC 5288 AES - GCM Cipher

This memo describes the use of the Advanced Encryption Standard (AES) in Galois/Counter Mode (GCM) as a Transport Layer Security (TLS) authenticated encryption operation. GCM provides both confidentiality and data origin authentication, can be efficiently implemented in hardware for speeds of 10 gigabits per second and above, and is also well-suited to software implementations. This memo define...

متن کامل

Faster and Timing-Attack Resistant AES-GCM

We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous implementations, while simultaneously offering protection against timing attacks. In particular, it is the only cache-timing-attack resistant implementation offering competitive speeds for stream as well as for packet ...

متن کامل

AES-GCM-SIV: Specification and Analysis

In this paper, we describe and analyze the security of the AES-GCM-SIV mode of operation, as defined in the CFRG specification [10]. This mode differs from the original GCM-SIV mode that was designed in [11] in two main aspects. First, the CTR encryption uses a 127-bit pseudo-random counter instead of a 95-bit pseudo-random value concatenated with a 32-bit counter. This construction leads to im...

متن کامل

An Efficient Fpga Implementation of Aes Algorithm

The Advanced Encryption Standard can be programmed in software or built with pure hardware. But Field Programmable Gate Arrays (FPGAS) offer a faster and more customizable solution, since the entire algorithm can be executed in a single tick of clock cycle. This research deals with the implementation of AES algorithm in FPGA using Verilog Language. Software is used for simulation and optimizati...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEICE Electronics Express

سال: 2018

ISSN: 1349-2543

DOI: 10.1587/elex.15.20180559